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ISL5216
TABLE 28. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 1 (IWA = *017h)
P(31:0)
31:24
23:16
15:8
7:0
P(31:0)
31:24
23:16
15:8
7:0
P(15:0)
N/A
P(15:0)
N/A
P(15:0)
N/A
P(15:0)
15:0
FUNCTION
Fourth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 23:16.
Third serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 23:16.
Second serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 15:8.
First serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 7:0.
TABLE 29. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 2 (IWA = *018h)
FUNCTION
Set to zero
Seventh serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 23:16.
Sixth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 15:8.
Fifth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 26 for functional description of bits 7:0.
TABLE 30. SOFTWARE RESET REGISTER (IWA = *019h)
FUNCTION
Writing to this location resets the following activities of the functional block indicated.
Input Format/Select, NCO, Mixer and CIC.
Clears any pending enable in each channel's input demultiplexer function, loads the CIC decimation counter (the load value
is indeterminate if the decimation counter preload register has not been loaded), clears all processing enables (stops all
processing in the data path, but does not clear the data path registers).
Filter Compute Engine:
Resets the Read/Write pointers, fetch instruction 31 and start the filter program execution.
AGC:
Resets the compute blocks in both the forward and loop filter blocks (any calculations in progress are lost).
Cartesian-to-Polar Coordinate Converter:
Resets the compute blocks (any calculations in progress are lost).
FIFO:
Resets counter (clears the FIFO, all data is lost).
Resampler Timing NCO:
Clears the slave (active) frequency registers and clears the phase accumulator.
Output Section:
Resets the serial output section (clears all registers, counters, and flags but does not clear the configuration registers).
Self Test Control:
Resets the self test control logic of the front end (Input Format/Select, NCO, Mixer, and CIC) and the back end (Filter Compute
Engine, AGC, and Cartesian-to-Polar Coordinate Converter).
TABLE 31. CHANNEL TIMING ADVANCE STROBE REGISTER (IWA = *01Ah)
FUNCTION
Writing to this location inserts one extra data sample in the CIC to FIR path by repeating a sample. Used for shifting the FIR filter
compute engine timing.
TABLE 32. CHANNEL TIMING RETARD STROBE Register (IWA = *01Bh)
FUNCTION
Writing to this location deletes one data sample in the CIC to FIR path. Used for shifting the FIR filter compute engine timing.
TABLE 33. CARRIER PHASE OFFSET (IWA = *01Ch)
FUNCTION
Carrier phase offset. Values of 0000H - FFFFH in this register represent phase shifts of 0 to 65535/65536 * 360 degrees (this value
may also be interpreted as a signed integer, in which case the range 8000H - 7FFFH corresponds to phase shifts of -180 to
32767/32768 * 180 degrees). For the HSP50216 backward compatibility, the original 3-bit phase offset (IWA *004 bits 8:6) is added
to the new 16-bit phase offset register. HSP50216 configurations use IWA *004. New configurations should set *004 bits 8:6 to zero
and use this register. This register is set to 0 by the reset pin.
42
FN6013.3
July 13, 2007
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